This invention relates to circuitry for enhancing the speed of transfer of information from one source to another and specifically for providing a bilateral path between two transceivers with separate circuitry in each leg of the path which selectively acts to amplify/level shift and/or acts as a one terminal negative capacitance generator which reduces capacitance loading and thus enhances response time.
Many of today's electronics systems use MOS circuitry which selectively has to drive a relatively high capacitance line (bus). One avenue to try and enhance response time is to increase the physical size of all the MOS drive devices so as to increase the drive capability by lowering the resistance. This also increases the capicitance on the bus which degrades response time. A point is reached at which increasing the size of the MOS driver devices proportionally increases the capacitance on the bus such that there is little or no enhancement of response time.
The publication entitled Applications of Operational Amplifier Third-Generation Techniques by Jerald Graeme (pp. 38-40), describes an amplifier which uses a capacitor coupled between an input terminal and the output terminal to cancel some of the parasitic capacitance associated with the input terminal of the amplifier. This serves to enhance the response time of the amplifier but does little to enhance the response time through a heavily capacitively loaded data bus which may be coupled to the output of the amplifier.
U.S. patent application Ser. No. 333,400, which is being filed concurrently with the present application and in which there is a common assignee and one common inventor, discloses essentially a one terminal negative capacitance generator circuit which can be coupled to a data bus (conductor) and acts to reduce the loading capacitance thereon. This serves to enhance the response time of information sent through the conductor.
It is desirable in many instances to provide a bilateral path between two transceivers which includes amplification and/or level shifting circuitry and in which capacitive loading on electrical conduits (data buses) connecting the transceivers is reduced such that response time is enhanced.